I am trying to implement OpenSPARCT1 on Xilinx Virtex-7(VC707 XC7VX485T-2FFG1761CES Evaluation Board), single core and multi core. I first tried the EDK project on Virtex-5 and now I want to check feasibility of implementation of the same on Virtex-7. But I am facing a few problems as below:
1. Generating NGC netlist for Virtex-7 - For rxil command, the OpenSPARCT1 package does not contain the .xst file for my Virtex-7 device. How can I create one or modify the others for my FPGA? Also I tried creating a project on ISE 13.4 and added a copy of all the files mentioned in /design/sys/iop/sparc/xst/sparc.flist but the synthesis is not running due to many missing files and unrecognized modules.
2. I earlier implemented the EDK project on Xilinx EDK 10.1. How can I make it run using Xilinx EDK 13.4? Previously it showed the error - ERROR:EDK:3548 - Revup to 13.4 failed
ERROR:EDK:3413 - Error(s) were encountered while updating your project.
Any inputs for solutions to the above problems would be highly appreciated.
I found a solution to my problem. I created a .xst file for virtex-7 device by copying device parameters given in a random ISE and I was able to generate the bit file for single-core 4-thread. It uses hardly 18½ LUT resources.
But still the EDK problem persists, if anyone has a solution, please contribute.
Also has anybody tried to implement a dual-core on single FPGA? I am trying to generate bit-file for dual core but I am not able to find options to do so. Please help!!