1 Reply Latest reply: Jul 5, 2013 4:30 AM by rukbat RSS

    Sun Fire V490 Memory Issue

    Dravidan

      Dear friend,

       

      while running the post in sunfire V490 server i received an error message a following.

      Done

      Executing POST w/%o0 = 0000.0800.0100.4041

      0:0> 

      0:0>@(#) Sun Fire[TM] V480/V490 POST 4.18.6 2005/11/03 18:04

             /export/delivery/delivery/4.18/4.18.6/post4.18.0/Camelot/cstone/integrate

      d  (root)

      0:0>Copyright © 2005 Sun Microsystems, Inc. All rights reserved

        SUN PROPRIETARY/CONFIDENTIAL.

        Use is subject to license terms.

      0:0>Jump from OBP->POST.

      0:0>Diag level set to MAX.

      0:0>Verbosity level set to NORMAL.

      0:0>

      0:0>Start selftest...

      0:0>CPUs present in system: 0:0 1:0 2:0 3:0

       

      ******  POST Running ******

       

      0:0>Test CPU(s)....Done

      0:0>Init Scan/I2C....Done

      0:0>Basic Memory Test....Done

      0:0>Full CPU Test....-0:0>Memory Block....|xxxx

      Done

      2:0>ERROR:      Unexpected Trap!

      2:0>H/W under test = Safari bus CPU 2, Motherboard/Centerplane

      2:0>Repair Instructions: Replace items in order listed by 'H/W under test' above

      .

      2:0>END_ERROR

      2:0>CPU 2 trap trace.

      2:0>    tl  tt         tstate                 tpc               tnpc

      2:0>    00  63  00000099.58001602  ffffffff.f0123b70  ffffffff.f0123b74

      2:0>    01  00  00000000.00000000  00000000.00000000  00000000.00000000

      2:0>    02  00  00000000.00000000  00000000.00000000  00000000.00000000

      2:0>    03  00  00000000.00000000  00000000.00000000  00000000.00000000

      2:0>    04  00  00000000.00000000  00000000.00000000  00000000.00000000

      2:0>AFAR=00000020.00109a00

      2:0>Clearing trap table.

      2:0>Invoking debug menu...

      2:0>    0       Peek/Poke interface

      2:0>    1       Dump DAR Error Bits

      2:0>    2       Dump Scan Chain

      2:0>    3       Dump CPU Regs

      2:0>    4       Dump BBC Regs

      2:0>    5       Dump Mem Controller Regs

      2:0>    6       Dump Valid DMMU entries

      2:0>    7       Dump IMMU entries

      2:0>    8       Dump Struct Info

      2:0>    9       Dump Mailbox

      2:0>    a       Dump IO-Bridge regs unit 0

      2:0>    b       Dump IO-Bridge regs unit 1

      2:0>    c       Allow other CPUs to print

      2:0>    d       Do soft reset

      2:0>    ?       Help

      2:0>

      2:0>Selection:c

      3:0>Pattern aaaaaaaa.aaaaaaaa up.

      0:0>Pattern 55555555.55555555 up.

      1:0>Pattern 55555555.55555555 up.

      3:0>Pattern 55555555.55555555 up.

      0:0>Pattern aaaaaaaa.aaaaaaaa down.

      1:0>Pattern aaaaaaaa.aaaaaaaa down.

      2:0>    0       Peek/Poke interface

      2:0>    1       Dump DAR Error Bits

      2:0>    2       Dump Scan Chain

      2:0>    3       Dump CPU Regs

      2:0>    4       Dump BBC Regs

      2:0>    5       Dump Mem Controller Regs

      2:0>    6       Dump Valid DMMU entries

      2:0>    7       Dump IMMU entries

      2:0>    8       Dump Struct Info

      2:0>    9       Dump Mailbox

      2:0>    a       Dump IO-Bridge regs unit 0

      2:0>    b       Dump IO-Bridge regs unit 1

      2:0>    c       Allow other CPUs to print

      2:0>    d       Do soft reset

      2:0>    ?       Help

      2:0>

      2:0>Selection:c

      3:0>Pattern aaaaaaaa.aaaaaaaa down.

      0:0>Pattern 55555555.55555555 down.

      1:0>Pattern 55555555.55555555 down.

      3:0>Pattern 55555555.55555555 down.

      0:0>Flush Caches

      2:0>    0       Peek/Poke interface

      2:0>    1       Dump DAR Error Bits

      2:0>    2       Dump Scan Chain

      2:0>    3       Dump CPU Regs

      2:0>    4       Dump BBC Regs

      2:0>    5       Dump Mem Controller Regs

      2:0>    6       Dump Valid DMMU entries

      2:0>    7       Dump IMMU entries

      2:0>    8       Dump Struct Info

      2:0>    9       Dump Mailbox

      2:0>    a       Dump IO-Bridge regs unit 0

      2:0>    b       Dump IO-Bridge regs unit 1

      2:0>    c       Allow other CPUs to print

      2:0>    d       Do soft reset

      2:0>    ?       Help

      2:0>

      2:0>Selection:c

      1:0>Get code in ecache.

      3:0>Get code in ecache.

      0:0>Get code in ecache.

      0:0>IO-Bridge Tests.....

      0:0>IO-Bridge unit 0 init      test

      0:0>SCH-0  Init all Registers  test

      0:0>

      0:0>SCH-0  Init Safari Regs    test   Safari

      0:0>sch_gen8_init 00000400.04410000 < 02555555.00800002

      0:0>sch_gen8_init 00000400.04000000 < fc000000.0011a953

      0:0>sch_gen8_init 00000400.04400008 < 000007fe.00000000

      0:0>sch_gen8_init 00000400.04400000 < 00000700.00000000

      0:0>sch_gen8_init 00000400.04400018 < 000007fe.00000000

      2:0>    0       Peek/Poke interface

      2:0>    1       Dump DAR Error Bits

      2:0>    2       Dump Scan Chain

      2:0>    3       Dump CPU Regs

      2:0>    4       Dump BBC Regs

      2:0>    5       Dump Mem Controller Regs

      2:0>    6       Dump Valid DMMU entries

      2:0>    7       Dump IMMU entries

      2:0>    8       Dump Struct Info

      2:0>    9       Dump Mailbox

      2:0>    a       Dump IO-Bridge regs unit 0

      2:0>    b       Dump IO-Bridge regs unit 1

      2:0>    c       Allow other CPUs to print

      2:0>    d       Do soft reset

      2:0>    ?       Help

      2:0>

      2:0>Selection:c

      0:0>sch_gen8_init 00000400.04400010 < 00000702.00000000

      0:0>sch_gen8_init 00000400.04400048 < 000007ff.00000000

      0:0>sch_gen8_init 00000400.04400040 < 800007fd.00000000

      0:0>sch_gen8_init 00000400.04400058 < 000007ff.fe000000

      0:0>sch_gen8_init 00000400.04400050 < 800007ff.ec000000

      0:0>sch_gen8_init 00000400.04400068 < 000007ff.00000000

      0:0>sch_gen8_init 00000400.04400060 < 800007fe.00000000

      0:0>sch_gen8_init 00000400.04400078 < 000007ff.fe000000

      0:0>sch_gen8_init 00000400.04400070 < 800007ff.ee000000

      0:0>sch_gen8_init 00000400.04417008 < 55555555.55555555

      0:0>sch_gen8_init 00000400.04417008 < aaaaaaaa.aaaaaaaa

      0:0>sch_gen8_init 00000400.04417008 < 00000000.00000000

      0:0>sch_gen8_init 00000400.04410018 < fc000000.00003ff7

      2:0>    0       Peek/Poke interface

      2:0>    1       Dump DAR Error Bits

      2:0>    2       Dump Scan Chain

      2:0>    3       Dump CPU Regs

      2:0>    4       Dump BBC Regs

      2:0>    5       Dump Mem Controller Regs

      2:0>    6       Dump Valid DMMU entries

      2:0>    7       Dump IMMU entries

      2:0>    8       Dump Struct Info

      2:0>    9       Dump Mailbox

      2:0>    a       Dump IO-Bridge regs unit 0

      2:0>    b       Dump IO-Bridge regs unit 1

      2:0>    c       Allow other CPUs to print

      2:0>    d       Do soft reset

      2:0>    ?       Help

      2:0>

      2:0>Selection:c

      0:0>sch_gen8_init 00000400.04410008 < 7c000000.00003ff7

      0:0>sch_gen8_init 00000400.04410010 < 00000000.00000000

      0:0>sch_gen8_init 00000400.04410020 < 80000000.00000000

      0:0>sch_gen8_init 00000400.04410030 < f8000000.00000000

      0:0>sch_gen8_init 00000400.04410040 < f8000000.00000000

      0:0> UPA REGister base = 00000400.04480000

      0:0>sch_gen8_init 00000400.04480000 < 00000000.01108000

      0:0>sch_gen8_init 00000400.04480008 < 00000000.01108000

      0:0>    PASSED

      0:0>SCH-0  Init PBM Regs       test   Port A

      0:0>sch_gen1_init 000007ff.ec000040 < 00

      0:0>sch_gen1_init 000007ff.ec000041 < 00

      0:0>sch_gen8_init 00000400.04602000 < 8008007c.0000003f

      2:0>    0       Peek/Poke interface

      2:0>    1       Dump DAR Error Bits

      2:0>    2       Dump Scan Chain

      2:0>    3       Dump CPU Regs

      2:0>    4       Dump BBC Regs

      2:0>    5       Dump Mem Controller Regs

      2:0>    6       Dump Valid DMMU entries

      2:0>    7       Dump IMMU entries

      2:0>    8       Dump Struct Info

      2:0>    9       Dump Mailbox

      2:0>    a       Dump IO-Bridge regs unit 0

      2:0>    b       Dump IO-Bridge regs unit 1

      2:0>    c       Allow other CPUs to print

      2:0>    d       Do soft reset

      2:0>    ?       Help

      2:0>

      2:0>Selection:

      --------------------------------------

       

      Kindly provide me the detailed issue and action i need to take

        • 1. Re: Sun Fire V490 Memory Issue

          You don't have a memory (RAM) issue.

          Your message already tells you what to do.

          The message says "Repair Instructions: Replace items in order listed by 'H/W under test' above."

          .

          The message clearly described that it was working on...

          "H/W under test = Safari bus CPU 2, Motherboard/Centerplane"

          Shut the system down, disassemble it, then re-seat or replace the centerplane.

           

          Alternatively, you could consider using your service contract privileges to log a support request (SR) with Oracle and get a service engineer to do that for you.