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5 Replies Latest reply: May 3, 2010 9:29 AM by 807576 RSS

OpenSPARC T1 Synthesis Errors

807576 Newbie
Currently Being Moderated
Hi All,

I am trying to run the OpenSPARC T1.1.7 synthesis out-of-the-box (i.e. I have no modified any of the RTL files) via:

rsyn -all

However, I have encountered the following errors:

================================
rsyn: Running synthesis for ctu
Abort at 51
Fatal: Internal System Error, cannot recover

rsyn: Running synthesis for jbi
Abort at 51
Fatal: Internal System Error, cannot recover

rsyn: Running synthesis for pads/pad_jbusl
/research/scrap/hy246/OpenSPARCT1.1.7/tools/bin/syn_command: line 25: 14330 Segmentation fault dc_shell-t -f $DV_ROOT/design/sys/synopsys/script/run.scr > dc_shell.log

rsyn: Running synthesis for pads/pad_jbusr
/research/scrap/hy246/OpenSPARCT1.1.7/tools/bin/syn_command: line 25: 14371 Segmentation fault dc_shell-t -f $DV_ROOT/design/sys/synopsys/script/run.scr > dc_shell.log
============================

I am wondering if this has happened before for anyone. It is puzzling that I am getting errors like this out-of-the-box. Every other module has synthesized uneventfully.

Further information:
Line 51 of the user_cfg.scr file for the ctu module is:
design/sys/iop/ctu/rtl/ctu_clsp_clkgn_clksel.v \

Line 51 of the user_cfg.scr file for the jbi module is:
design/sys/iop/jbi/jbi_min/rtl/jbi_min_rq.v

I assume that these are the lines in question for ctu and jbi. I am not certain about what files would help with fixing the seg fault, but am more than happy to fetch it if someone wishes to help.

Thanks in Advance,
hy246
  • 1. Re: OpenSPARC T1 Synthesis Errors
    807576 Newbie
    Currently Being Moderated
    Can you share what hardware platform and the OS version you are using. Also share which Synopsys DC version you are using.

    You will have to check the log files under specific blocks failing (e.g. ctu/synopsys/dc_shell.log) to see if there are any errors there.

    PS - I just synthesized v1.7 ctu and jbi on SPARC/Solaris with synopsys,vZ-2007.03 and things worked just fine.
  • 2. Re: OpenSPARC T1 Synthesis Errors
    807576 Newbie
    Currently Being Moderated
    I am not sure what parts are relevant in the dc_shell file, since the most obviously error message part simply tells me to complain to Synopsys. A bit of the end of my dc_shell.log for ctu follows:

    ==================================================================
    Current design is 'ctu_clsp_synch_cljl'.
    Loading verilog file '/research/scrap/hy246/OpenSPARCT1.1.7/design/sys/iop/ctu/rtl/ctu_clsp_synch_dldg.v'
    Detecting input file type automatically (-rtl or -netlist).
    Running DC verilog reader
    Opening include file /research/scrap/hy246/OpenSPARCT1.1.7/design/sys/iop/include/sys.h


    The tool has just encountered a fatal error:

    If you encountered this fatal error when using the most recent
    Synopsys release, submit this stack trace and a test case that
    reproduces the problem to the Synopsys Support Center by using
    Enter A Call at http://solvnet.synopsys.com/EnterACall.

    * For information about the latest software releases, go to the Synopsys
    SolvNet Release Library at http://solvnet.synopsys.com/ReleaseLibrary.

    * For information about required Operating System patches, go to
    http://www.synopsys.com/qrsc.

    * For instructions for creating, packaging, and sending a test case, go to
    http://www.synopsys.com/testcase.

    Release = 'B-2008.09-SP5' Architecture = 'linux' Program = 'dc_shell'

    '233520084 233520663 -6912 -2811756 233869373 204929890 192609417 191567077 189171107 189158651 188902043 162164149 162169360 162250216 162274797 162309914 183855928 183852452 183275694 194386238 190928675 190809403 191139495 188899864 188900338 194389833 194390137 182414289 182191405 147368759 147372695 147374821 147377597 147484414 149348802 233259298 234792794 234798874 234957938 234979317 234802903 234822394 234798874 234799712 233227030 233239409 233259298 234792794 234798874 234799712 233252141 233252702 145947996 145948141 145966559 145968800 145970108 134620827 134606714 11247244'
    ====================================================================


    For jbi:

    ================================================
    Current design is 'jbi_jbus_arb'.
    Loading verilog file '/research/scrap/hy246/OpenSPARCT1.1.7/design/sys/iop/jbi/jbi_mout/rtl/jbi_jid_to_yid_pool.v'
    Detecting input file type automatically (-rtl or -netlist).
    Running DC verilog reader
    Opening include file /research/scrap/hy246/OpenSPARCT1.1.7/design/sys/iop/include/sys.h


    The tool has just encountered a fatal error:

    If you encountered this fatal error when using the most recent
    Synopsys release, submit this stack trace and a test case that
    reproduces the problem to the Synopsys Support Center by using
    Enter A Call at http://solvnet.synopsys.com/EnterACall.

    * For information about the latest software releases, go to the Synopsys
    SolvNet Release Library at http://solvnet.synopsys.com/ReleaseLibrary.

    * For information about required Operating System patches, go to
    http://www.synopsys.com/qrsc.

    * For instructions for creating, packaging, and sending a test case, go to
    http://www.synopsys.com/testcase.

    Release = 'B-2008.09-SP5' Architecture = 'linux' Program = 'dc_shell'

    '233520084 233520663 -6912 -1287676 233869373 204929890 192609417 191567077 189171107 189158651 188902043 162164149 162169360 162250216 162274797 162309914 183855928 183852452 183275694 194386238 190928675 190809403 191139495 188899864 188900338 194389833 194390137 182414289 182191405 147368759 147372695 147374821 147377597 147484414 149348802 233259298 234792794 234798874 234957938 234979317 234802903 234822394 234798874 234799712 233227030 233239409 233259298 234792794 234798874 234799712 233252141 233252702 145947996 145948141 145966559 145968800 145970108 134620827 134606714 11247244'
    ==========================================================================

    Perhaps the version of Synopsys I am using is insufficient or buggy? I am running the synthesis on an x86_64 Xeon machine running Redhat Linux
    2.6.18-92.1.22.el5.

    Thank you for helping. Please let me know ASAP if you need the entire log file or more information.

    - hy246
  • 3. Re: OpenSPARC T1 Synthesis Errors
    807576 Newbie
    Currently Being Moderated
    Hi hy246

    Did you ever find out the solution to this problem because I am also having the same problem

    I am trying to run the synthesis on an i7 32Gb Server running RedHat CentOS release 5.3 (Final)

    Thanks

    Dan
  • 4. Re: OpenSPARC T1 Synthesis Errors
    807576 Newbie
    Currently Being Moderated
    Hi

    Was this problem ever solved because I am having the same problem.

    In my log I get:

    Loading verilog file '/opt/fastcad/disktmp/dcn1v07/OpenSPARC/design/sys/iop/ctu/rtl/ctu_clsp_synch_dldg.v'
    Detecting input file type automatically (-rtl or -netlist).
    Running DC verilog reader
    Opening include file /opt/fastcad/disktmp/dcn1v07/OpenSPARC/design/sys/iop/include/sys.h

    Release = 'C-2009.06-SP4' Architecture = 'amd64' Program = 'dc_shell'
    Exec = '/home/esdcad/software/synopsys/linux/galaxy_C-2009.06-SP4/amd64/syn/bin/common_shell_exec'

    '104048025 104049688 104171401 104417992 75711469 65325089 64449783 61829722 61817577 61541311 33961942 33979641 34050276 34050478 34073921 56224269 56221004 56194520 67037598 63641027 63608230 66243627 63736539 61539070 61539562 67040825 67041246 55600837 55388968 18991701 18995328 18997189 18999838 19098977 20792432 103790337 105560751 105566418 105716569 105735606 105570516 105588117 105566418 105567263 103759745 103771575 103790337 105560751 105566418 105567263 103782983 103783627 17739007 17755488 17757558 17758810 4336253 4323101 250104371572'

    I have tried by invoking both the 64 bit and 32 bit versions.... I have even tried the T2 rsyn tool command and had no luck with that either

    I have access to both galaxy_C-2009.06-SP4 and galaxy_B-2008.09-SP4 on a 32Gb i7 server running RedHat.

    Thanks alot

    Dan
  • 5. Re: OpenSPARC T1 Synthesis Errors
    807576 Newbie
    Currently Being Moderated
    HI

    I sorted this error it has to do with the fact that the read_file function in DC "Cannot pass parameters (must use directives in HDL)" as documented in table 6-2 of this pdf file http://www.vlsiip.com/dc_shell/dcug_6.pdf this means that the scripts for JBI and CTU must be edited. So with the CTU module the file ctu_revision.v has to be excluded from the "rtl_files" list at the top of the user_cfg.scr script (found in... /design/sys/iop/ctu/synopsys/script directory) and the following lines added at the bottom of the script:

    read_file -format verilog -define RUNDC $dv_root/design/sys/iop/ctu/rtl/ctu_jtag_id.v
    analyze -format verilog $dv_root/design/sys/iop/ctu/rtl/ctu_jtag_id.v
    elaborate ctu_jtag_id

    read_file -format verilog -define RUNDC $dv_root/design/sys/iop/ctu/rtl/ctu_mask_id.v
    analyze -format verilog $dv_root/design/sys/iop/ctu/rtl/ctu_mask_id.v
    elaborate ctu_mask_id

    read_file -format verilog -define RUNDC $dv_root/design/sys/iop/ctu/rtl/ctu_revision.v
    analyze -format verilog $dv_root/design/sys/iop/ctu/rtl/ctu_revision.v
    elaborate ctu_revision


    so the final CTU script is as follows:

    # ========== Copyright Header Begin ==========================================
    #
    # OpenSPARC T1 Processor File: user_cfg.scr
    # Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
    # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
    #
    # The above named program is free software; you can redistribute it and/or
    # modify it under the terms of the GNU General Public
    # License version 2 as published by the Free Software Foundation.
    #
    # The above named program is distributed in the hope that it will be
    # useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
    # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
    # General Public License for more details.
    #
    # You should have received a copy of the GNU General Public
    # License along with this work; if not, write to the Free Software
    # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
    #
    # ========== Copyright Header End ============================================

    source -echo -verbose $dv_root/design/sys/synopsys/script/project_io_cfg.scr

    set rtl_files {\

    lib/u1/u1.behV \
    lib/m1/m1.behV \
    design/sys/iop/common/rtl/swrvr_clib.v \
    design/sys/iop/ctu/rtl/ctu_mask_id.v\
    design/sys/iop/ctu/rtl/ctu_jtag_id.v \
    design/sys/iop/common/rtl/ucb_noflow.v \
    design/sys/iop/common/rtl/ucb_bus_in.v \
    design/sys/iop/common/rtl/ucb_bus_out.v \
    design/sys/iop/ctu/common/rtl/ctu_lib.v \
    design/sys/iop/ctu/common/rtl/ctu_sync_header.v \
    design/sys/iop/common/rtl/cluster_header_sync.v \
    design/sys/iop/ctu/rtl/ctu_clsp_clkgn_syncp.v \
    design/sys/iop/ctu/rtl/ctu_clsp_clkgn_shadreg.v \
    design/sys/iop/ctu/rtl/ctu_clsp_clkgn.v \
    design/sys/iop/ctu/rtl/ctu_clsp_dramgif.v \
    design/sys/iop/ctu/rtl/ctu_clsp_jbusgif.v \
    design/sys/iop/ctu/rtl/ctu_clsp_cmpgif.v \
    design/sys/iop/ctu/rtl/ctu_clsp_creg.v \
    design/sys/iop/ctu/rtl/ctu_clsp_clkctrl.v \
    design/sys/iop/ctu/rtl/ctu_clsp_ctrl.v \
    design/sys/iop/ctu/rtl/ctu_clsp_pllcnt.v \
    design/sys/iop/ctu/rtl/ctu_dft_jtag_tap.v \

    design/sys/iop/ctu/rtl/ctu_clsp_clkgn_ssiclk.v \
    design/sys/iop/ctu/rtl/ctu_clsp_clkgn_nstep.v \
    design/sys/iop/ctu/rtl/ctu_clsp_clkgn_nstep_cnt.v \
    design/sys/iop/ctu/rtl/ctu_clsp_clkgn_clksel.v \
    design/sys/iop/ctu/rtl/ctu_clsp_clkgn_clksw.v \
    design/sys/iop/ctu/rtl/ctu_clsp_synch_jlcl.v \
    design/sys/iop/ctu/rtl/ctu_clsp_synch_jldl.v \
    design/sys/iop/ctu/rtl/ctu_clsp_synch_cljl.v \
    design/sys/iop/ctu/rtl/ctu_clsp_clkgn_fstlog.v \
    design/sys/iop/ctu/rtl/ctu_clsp_clkgn_ddiv.v \
    design/sys/iop/ctu/rtl/ctu_test_stub_scan.v \
    design/sys/iop/ctu/rtl/ctu_clsp.v \
    design/sys/iop/ctu/rtl/ctu_dft_jtag.v \
    design/sys/iop/ctu/rtl/ctu_dft_bist.v \
    design/sys/iop/ctu/rtl/ctu_dft_creg.v \
    design/sys/iop/ctu/rtl/ctu_dft.v \

    design/sys/iop/analog/bw_rng/rtl/bw_rng.v \
    design/sys/iop/analog/bw_pll/rtl/bw_pll.v \
    design/sys/iop/analog/bw_tsr/rtl/bw_tsr.v \

    design/sys/iop/common/rtl/cluster_header_ctu.v \
    design/sys/iop/common/rtl/sync_pulse_synchronizer.v \

    design/sys/iop/ctu/common/rtl/bw_clk_cl_ctu_jbus.v \
    design/sys/iop/ctu/common/rtl/bw_clk_cl_ctu_cmp.v \
    design/sys/iop/ctu/common/rtl/bw_clk_cl_ctu_2xcmp.v \
    design/sys/iop/ctu/common/rtl/bw_clk_cl_ctu_2xcmp_b.v \
    design/sys/iop/ctu/common/rtl/bw_ctu_clk_sync_mux.v \
    design/sys/iop/analog/bw_clk/rtl/bw_clk_cclk_sync.v \
    design/sys/iop/ctu/common/rtl/bw_zzctu_sync.v \
    design/sys/iop/ctu/rtl/ctu_clsp_synch_dldg.v \
    design/sys/iop/ctu/rtl/ctu_clsp_clkgn_1div.v \

    design/sys/iop/common/rtl/synchronizer_asr.v \

    design/sys/iop/ctu/rtl/ctu.v \
    }

    set mix_files {}
    set top_module ctu

    set include_paths {\
    design/sys/iop/include \
    design/sys/iop/ctu/include \
    design/sys/iop/ctu/rtl \
    design/sys/iop/ctu/common/rtl \
    }

    set black_box_libs {}
    set black_box_designs {}
    set mem_libs {}
    set dont_touch_modules {}
    set compile_effort "medium"

    set compile_flatten_all 1

    set compile_no_new_cells_at_top_level false

    set default_clk cmp_gclk
    set default_clk_freq 1200
    set default_setup_skew 0.1
    set default_hold_skew 0.1
    set default_clk_transition 0.04
    set clk_list {                        \
    {cmp_gclk   1200.0   0.100   0.100   0.040} \
    {jbus_gclk   240.0   0.375 0.080 0.050} \
    }

    set ideal_net_list {}
    set false_path_list {}
    set enforce_input_fanout_one 0
    set allow_outport_drive_innodes 1
    set skip_scan 0
    set add_lockup_latch false
    set chain_count 1
    set scanin_port_list {}
    set scanout_port_list {}
    set scanenable_port global_shift_enable
    set has_test_stub 1
    set scanenable_pin test_stub_no_bist/se
    set long_chain_so_0_net long_chain_so_0
    set short_chain_so_0_net short_chain_so_0
    set so_0_net so_0
    set insert_extra_lockup_latch 0
    set extra_lockup_latch_clk_list {}

    read_file -format verilog -define RUNDC $dv_root/design/sys/iop/ctu/rtl/ctu_jtag_id.v
    analyze -format verilog $dv_root/design/sys/iop/ctu/rtl/ctu_jtag_id.v
    elaborate ctu_jtag_id

    read_file -format verilog -define RUNDC $dv_root/design/sys/iop/ctu/rtl/ctu_mask_id.v
    analyze -format verilog $dv_root/design/sys/iop/ctu/rtl/ctu_mask_id.v
    elaborate ctu_mask_id

    read_file -format verilog -define RUNDC $dv_root/design/sys/iop/ctu/rtl/ctu_revision.v
    analyze -format verilog $dv_root/design/sys/iop/ctu/rtl/ctu_revision.v
    elaborate ctu_revision


    ******* the same fixes should work for JBI I guess but you will have to do the read analyze and elaborate the files jbi_dbg_buf.v and jbi_ncio_prtq_buf.v I believe (where there are instantiations of bw_rf_16x81 and bw_rf_16x65 with the parameter #(1,1,1,0)********

    use: find . -name "*.v" -print | xargs grep -R "#(1, 1, 1, 0)" to find them.

    however I have not tried this as I am working to a very close deadline and I am using the Megacells provided in the Synopsys Generic 90nm Library


    Hope this solves your problem if your looking at this topic!



    Dan

    Edited by: dan_nevill on May 2, 2010 4:11 PM

    Edited by: dan_nevill on May 3, 2010 9:26 AM