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1 Reply Latest reply: May 3, 2010 6:58 AM by 807576 RSS

OpenSPARCT1 synthesis

807576 Newbie
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Hi All,

I am trying to synthesis the OpenSPARCT1 processor on ASIC, so I want to ask if any one has done this before, and is it applicable?. And does any one have a modified SRAMs RTL code that uses ASIC vendor memory generators so I can start with as a reference. And has any one made a gatesim simulation as mentioned in the manuals using vector playback mechanism? And do any one know how to initialize all the arrays in the processor to avoid the mismatches as mentioned in the manual? and did any one write a script to do that? Here is the part in the manual that talks about array intialization:

Caution – Running this vector playback mechanism on RTL, although feasible, is
not recommended due to some array initialization issues. In the gate playback mode,
all arrays are explicitly initialized to zero while in RTL and some arrays are
initialized to random values. This may result in mismatch in playback simulation. If
RTL arrays are initialized correctly (zeros) then this mechanism can be used to verify
RTL netlist as well.

Sorry for all of this questions as I am a newbie.
Any help regarding this matter is highly appreciated. And thanks in advance.