1 Reply Latest reply: Apr 24, 2010 6:00 PM by 807576 RSS

    TOP LEVEL SYNTHESIS EXAMPLE

    807576
      Hi all,

      I used rsyn to synthesize block level modules for opensparc t1. Unfortunately I cannot seem to figure out a way to generate top-level (inter-mediate hierarchical files). I went through all the threads of the forum and most of the suggested ways is to use something semi-automatic. where we make verilog from block level to cluster level and then to cpu level.

      Example:

      First stage:
      use fpu_add, fpu_mul......etc (blocks synthesized by rysn) and then make fpu.
      Second stage:
      use fpu, ccx (from first stage) ... to make 8 core T1 (top level).

      While the idea is great I cannot figure out how to do it. An example would be great.


      If anyone can post an example script : maybe how to make FPU from its sub-blocks (fpu_add, fpu_mul, fpu_div)... etc it would be of great help.


      I understood the method other guys suggested to make top-level verilogs but what I need is an example. Please help guys
        • 1. Re: TOP LEVEL SYNTHESIS EXAMPLE
          807576
          Well,

          I found this link:

          http://www.opensparc.net/courses/synopsys/synthesizing-opensparc-using-90nm-library.html

          it tells exactly an example to generate FPU from its sub-modules. One synthesis method (method 1) looks at sub-modules generated by rsyn command the other (method 2) looks at all files located in fpu/rtl.

          I used method 1 to generate ccx. But every time i do this I have to look at unresolved references in link command during synthesis. And then search for RTL files which can resolve them.


          Is there an exact method by which I can generate these RTL's to be read without manually finding unlinked references. Anybody with experience please help.