I'm a student who is working on power modeling project
And I was suggested to use SPARC architecture which needs synthesis and simulation of OpenSPARC T1
So I started synthesis and was able to synthesize individual blocks successfully on Synopsys DCCompiler
Now I want to simulate the netlist using modelsim
The problem is I am not able to give proper inputs to the signals of vhdl test benches.(like inq signals of fpu_add )
Please suggest me where I can get the detailed explanation about the signals and various test cases for them
Thankyou in advance
P.S. : I tried enough with the test cases provided by OpenSPARC but VERA has some compatibility issues with Linux... As of now I want to know inputs for fpu_add module.