Infrastructure Software

hello,

I bought a sun enterprise 4500 to run java applications.
However I failed to boot on the CDROM to install solaris 10. In fact the CDROM is powered but I can not see in the system and I can't access it. It is the same thing with the harddrives in the disk board.
The system has 12 Sparc II 400 CPUs and 12Go so :
6 boards CPUs/Mem
1 Disk board with 2 disks with 18Go
1 CDROM
I have checked the SCSI plug and the disk board is in slot 3.
The SCSI cable is fine ...

I tried some OpenBoot command :
probe-scsi -> it gives nothing !!!
probe-scsi-all -> /sbus@3,0/SUNW,fas@3,8800000/

The only problem that I see is the clock board which has an orange led and following the documentation it seems that the board is not running well.

I start to be nuts.


I gives the test log files of the system when it starts and I have seen that the diskboard is recognized and tested but I can not access it through the Openboot ...

Any idea before I panic :) , please ?

Regards
Seb

LogFile :
0,0>Board 0 Cross Calls Test
0,0> Cross Calls Test
0,0>Displaying PROM Versions
0,0>Slot 0 CPU/Memory OBP 3.2.30 2002/10/25 14:03 POST 3.9.30 2002/10/25 14:04
0,0>Slot 1 IO Type 4 FCODE 1.8.27 2000/8/18 11:14 iPOST 3.4.27 2000/8/18 11:18
0,0>Slot 2 CPU/Memory OBP 3.2.30 2002/10/25 14:03 POST 3.9.30 2002/10/25 14:04
0,0>Slot 4 CPU/Memory OBP 3.2.30 2002/10/25 14:03 POST 3.9.30 2002/10/25 14:04
0,0>Slot 5 CPU/Memory OBP 3.2.30 2002/10/25 14:03 POST 3.9.30 2002/10/25 14:04
0,0>Slot 6 CPU/Memory OBP 3.2.30 2002/10/25 14:03 POST 3.9.30 2002/10/25 14:04
0,0>Slot 7 CPU/Memory OBP 3.2.30 2002/10/25 14:03 POST 3.9.30 2002/10/25 14:04
0,0>Board 0 Environmental Probe Test
0,0> Environmental Probe
0,0>Checking Power Supply Configuration
0,0>Power is more than adequate, load 7 ps 5
0,0>Reconfig memory due to POR or CLOCK RESET
0,0>Reconfig memory due to DIAG_LEVEL
0,0>Board 0 Probing Memory SIMMS Test
0,0> Probe SIMMID
0,0> Populated Memory Bank Status
0,0> bd # Size Address Way Status
0,0> 0 1024 Normal
0,0> 0 1024 Normal
0,0> 2 1024 Normal
0,0> 2 1024 Normal
0,0> 4 1024 Normal
0,0> 4 1024 Normal
0,0> 5 1024 Normal
0,0> 5 1024 Normal
0,0> 6 1024 Normal
0,0> 6 1024 Normal
0,0> 7 1024 Normal
0,0> 7 1024 Normal
0,0>Board 0 Memory Configuration Test
0,0> Memory Interleaving
0,0> Total banks with 8MB SIMMs = 0
0,0> Total banks with 32MB SIMMs = 0
0,0> Total banks with 128MB SIMMs = 12
0,0> Total banks with 256MB SIMMs = 0
0,0> Overall memory default speed = 60ns
0,0>Do OPTIMAL INTLV
0,0> Board 0 AC rev 5 RCTIME = 1 (Tras 71)
0,0> Board 2 AC rev 5 RCTIME = 1 (Tras 71)
0,0> Board 4 AC rev 5 RCTIME = 1 (Tras 71)
0,0> Board 5 AC rev 5 RCTIME = 1 (Tras 71)
0,0> Board 6 AC rev 5 RCTIME = 1 (Tras 71)
0,0> Board 7 AC rev 5 RCTIME = 1 (Tras 71)
0,0> Board 0 AC rev 5 RCTIME = 1 (Tras 71)
0,0> Board 2 AC rev 5 RCTIME = 1 (Tras 71)
0,0> Board 4 AC rev 5 RCTIME = 1 (Tras 71)
0,0> Board 5 AC rev 5 RCTIME = 1 (Tras 71)
0,0> Board 6 AC rev 5 RCTIME = 1 (Tras 71)
0,0> Board 7 AC rev 5 RCTIME = 1 (Tras 71)
0,0> Memory Refresh Enable
0,0>Board 0 SIMMs Test
0,0> MP Memory SIMM Clear Test
0,0> Memory Size is 12288Mbytes
0,0> CPU MID 1 clearing 00000000.00004000 to 00000000.40000000
0,0> CPU MID 4 clearing 00000000.40000000 to 00000000.80000000
0,0> CPU MID 5 clearing 00000000.80000000 to 00000000.c0000000
0,0> CPU MID 8 clearing 00000000.c0000000 to 00000001.00000000
0,0> CPU MID 9 clearing 00000001.00000000 to 00000001.40000000
0,0> CPU MID 10 clearing 00000001.40000000 to 00000001.80000000
0,0> CPU MID 11 clearing 00000001.80000000 to 00000001.c0000000
0,0> CPU MID 12 clearing 00000001.c0000000 to 00000002.00000000
0,0> CPU MID 13 clearing 00000002.00000000 to 00000002.40000000
0,0> CPU MID 14 clearing 00000002.40000000 to 00000002.80000000
0,0> CPU MID 15 clearing 00000002.80000000 to 00000002.c0000000
0,0> CPU MID 0 clearing 00000002.c0000000 to 00000003.00000000
0,0> CPU MID 0 clearing 00000000.00000000 to 00000000.00004000
0,0> Memory Walking Rows and Columns Test
0,0> MP Memory SIMM (6N RAM Patterns) Test
0,0> Memory Size is 12288Mbytes
0,0> CPU MID 1 testing 00000000.00000000 to 00000000.40000000
0,0> CPU MID 4 testing 00000000.40000000 to 00000000.80000000
0,0> CPU MID 5 testing 00000000.80000000 to 00000000.c0000000
0,0> CPU MID 8 testing 00000000.c0000000 to 00000001.00000000
0,0> CPU MID 9 testing 00000001.00000000 to 00000001.40000000
0,0> CPU MID 10 testing 00000001.40000000 to 00000001.80000000
0,0> CPU MID 11 testing 00000001.80000000 to 00000001.c0000000
0,0> CPU MID 12 testing 00000001.c0000000 to 00000002.00000000
0,0> CPU MID 13 testing 00000002.00000000 to 00000002.40000000
0,0> CPU MID 14 testing 00000002.40000000 to 00000002.80000000
0,0> CPU MID 15 testing 00000002.80000000 to 00000002.c0000000
0,0> CPU MID 0 testing 00000002.c0000000 to 00000003.00000000
0,0> MP Memory SIMM (moving inverse) Test
0,0> Memory Size is 12288Mbytes
0,0> CPU MID 1 testing 00000000.00000000 to 00000000.40000000
0,0> CPU MID 4 testing 00000000.40000000 to 00000000.80000000
0,0> CPU MID 5 testing 00000000.80000000 to 00000000.c0000000
0,0> CPU MID 8 testing 00000000.c0000000 to 00000001.00000000
0,0> CPU MID 9 testing 00000001.00000000 to 00000001.40000000
0,0> CPU MID 10 testing 00000001.40000000 to 00000001.80000000
0,0> CPU MID 11 testing 00000001.80000000 to 00000001.c0000000
0,0> CPU MID 12 testing 00000001.c0000000 to 00000002.00000000
0,0> CPU MID 13 testing 00000002.00000000 to 00000002.40000000
0,0> CPU MID 14 testing 00000002.40000000 to 00000002.80000000
0,0> CPU MID 15 testing 00000002.80000000 to 00000002.c0000000
0,0> CPU MID 0 testing 00000002.c0000000 to 00000003.00000000
0,0>Slave CPU Functional Tests
0,0> Slave CPU MID 1 started
0,1>Board 0 Functional CPU 1 Test
0,1> Dcache Init
0,1> Dcache Enable Test
0,1> Dcache Functionality Test
0,1> Ecache Stress Test
0,1> Ecache Functional Test
0,1> CPU Dispatch (Multi-Scalar) Test
0,1> SPARC Atomic Instructions Test
0,1> SPARC Prefetch Instructions Test
0,1> CPU Softint Registers and Interrupts Test
0,1> Uni-Processor Cache Coherence Test
0,1> Branch Memory Test
0,1> SDB ECC CE Test
0,1> SDB ECC Uncorrectable Test
0,1> FPU Instruction Test
0,0> Slave CPU MID 4 started
2,0>Board 2 Functional CPU 0 Test
2,0> Dcache Init
2,0> Dcache Enable Test
2,0> Dcache Functionality Test
2,0> Ecache Stress Test
2,0> Ecache Functional Test
2,0> CPU Dispatch (Multi-Scalar) Test
2,0> SPARC Atomic Instructions Test
2,0> SPARC Prefetch Instructions Test
2,0> CPU Softint Registers and Interrupts Test
2,0> Uni-Processor Cache Coherence Test
2,0> Branch Memory Test
2,0> SDB ECC CE Test
2,0> SDB ECC Uncorrectable Test
2,0> FPU Instruction Test
0,0> Slave CPU MID 5 started
2,1>Board 2 Functional CPU 1 Test
2,1> Dcache Init
2,1> Dcache Enable Test
2,1> Dcache Functionality Test
2,1> Ecache Stress Test
2,1> Ecache Functional Test
2,1> CPU Dispatch (Multi-Scalar) Test
2,1> SPARC Atomic Instructions Test
2,1> SPARC Prefetch Instructions Test
2,1> CPU Softint Registers and Interrupts Test
2,1> Uni-Processor Cache Coherence Test
2,1> Branch Memory Test
2,1> SDB ECC CE Test
2,1> SDB ECC Uncorrectable Test
2,1> FPU Instruction Test
0,0> Slave CPU MID 8 started
4,0>Board 4 Functional CPU 0 Test
4,0> Dcache Init
4,0> Dcache Enable Test
4,0> Dcache Functionality Test
4,0> Ecache Stress Test
4,0> Ecache Functional Test
4,0> CPU Dispatch (Multi-Scalar) Test
4,0> SPARC Atomic Instructions Test
4,0> SPARC Prefetch Instructions Test
4,0> CPU Softint Registers and Interrupts Test
4,0> Uni-Processor Cache Coherence Test
4,0> Branch Memory Test
4,0> SDB ECC CE Test
4,0> SDB ECC Uncorrectable Test
4,0> FPU Instruction Test
0,0> Slave CPU MID 9 started
4,1>Board 4 Functional CPU 1 Test
4,1> Dcache Init
4,1> Dcache Enable Test
4,1> Dcache Functionality Test
4,1> Ecache Stress Test
4,1> Ecache Functional Test
4,1> CPU Dispatch (Multi-Scalar) Test
4,1> SPARC Atomic Instructions Test
4,1> SPARC Prefetch Instructions Test
4,1> CPU Softint Registers and Interrupts Test
4,1> Uni-Processor Cache Coherence Test
4,1> Branch Memory Test
4,1> SDB ECC CE Test
4,1> SDB ECC Uncorrectable Test
4,1> FPU Instruction Test
0,0> Slave CPU MID 10 started
5,0>Board 5 Functional CPU 0 Test
5,0> Dcache Init
5,0> Dcache Enable Test
5,0> Dcache Functionality Test
5,0> Ecache Stress Test
5,0> Ecache Functional Test
5,0> CPU Dispatch (Multi-Scalar) Test
5,0> SPARC Atomic Instructions Test
5,0> SPARC Prefetch Instructions Test
5,0> CPU Softint Registers and Interrupts Test
5,0> Uni-Processor Cache Coherence Test
5,0> Branch Memory Test
5,0> SDB ECC CE Test
5,0> SDB ECC Uncorrectable Test
5,0> FPU Instruction Test
0,0> Slave CPU MID 11 started
5,1>Board 5 Functional CPU 1 Test
5,1> Dcache Init
5,1> Dcache Enable Test
5,1> Dcache Functionality Test
5,1> Ecache Stress Test
5,1> Ecache Functional Test
5,1> CPU Dispatch (Multi-Scalar) Test
5,1> SPARC Atomic Instructions Test
5,1> SPARC Prefetch Instructions Test
5,1> CPU Softint Registers and Interrupts Test
5,1> Uni-Processor Cache Coherence Test
5,1> Branch Memory Test
5,1> SDB ECC CE Test
5,1> SDB ECC Uncorrectable Test
5,1> FPU Instruction Test
0,0> Slave CPU MID 12 started
6,0>Board 6 Functional CPU 0 Test
6,0> Dcache Init
6,0> Dcache Enable Test
6,0> Dcache Functionality Test
6,0> Ecache Stress Test
6,0> Ecache Functional Test
6,0> CPU Dispatch (Multi-Scalar) Test
6,0> SPARC Atomic Instructions Test
6,0> SPARC Prefetch Instructions Test
6,0> CPU Softint Registers and Interrupts Test
6,0> Uni-Processor Cache Coherence Test
6,0> Branch Memory Test
6,0> SDB ECC CE Test
6,0> SDB ECC Uncorrectable Test
6,0> FPU Instruction Test
0,0> Slave CPU MID 13 started
6,1>Board 6 Functional CPU 1 Test
6,1> Dcache Init
6,1> Dcache Enable Test
6,1> Dcache Functionality Test
6,1> Ecache Stress Test
6,1> Ecache Functional Test
6,1> CPU Dispatch (Multi-Scalar) Test
6,1> SPARC Atomic Instructions Test
6,1> SPARC Prefetch Instructions Test
6,1> CPU Softint Registers and Interrupts Test
6,1> Uni-Processor Cache Coherence Test
6,1> Branch Memory Test
6,1> SDB ECC CE Test
6,1> SDB ECC Uncorrectable Test
6,1> FPU Instruction Test
0,0> Slave CPU MID 14 started
7,0>Board 7 Functional CPU 0 Test
7,0> Dcache Init
7,0> Dcache Enable Test
7,0> Dcache Functionality Test
7,0> Ecache Stress Test
7,0> Ecache Functional Test
7,0> CPU Dispatch (Multi-Scalar) Test
7,0> SPARC Atomic Instructions Test
7,0> SPARC Prefetch Instructions Test
7,0> CPU Softint Registers and Interrupts Test
7,0> Uni-Processor Cache Coherence Test
7,0> Branch Memory Test
7,0> SDB ECC CE Test
7,0> SDB ECC Uncorrectable Test
7,0> FPU Instruction Test
0,0> Slave CPU MID 15 started
7,1>Board 7 Functional CPU 1 Test
7,1> Dcache Init
7,1> Dcache Enable Test
7,1> Dcache Functionality Test
7,1> Ecache Stress Test
7,1> Ecache Functional Test
7,1> CPU Dispatch (Multi-Scalar) Test
7,1> SPARC Atomic Instructions Test
7,1> SPARC Prefetch Instructions Test
7,1> CPU Softint Registers and Interrupts Test
7,1> Uni-Processor Cache Coherence Test
7,1> Branch Memory Test
7,1> SDB ECC CE Test
7,1> SDB ECC Uncorrectable Test
7,1> FPU Instruction Test
0,0>Board 0 Functional CPU 0 Test
0,0> Dcache Init
0,0> Dcache Enable Test
0,0> Dcache Functionality Test
0,0> Ecache Stress Test
0,0> Ecache Functional Test
0,0> CPU Dispatch (Multi-Scalar) Test
0,0> SPARC Atomic Instructions Test
0,0> SPARC Prefetch Instructions Test
0,0> CPU Softint Registers and Interrupts Test
0,0> Uni-Processor Cache Coherence Test
0,0> Branch Memory Test
0,0> SDB ECC CE Test
0,0> SDB ECC Uncorrectable Test
0,0> FPU Instruction Test
0,0>TESTING IO BOARD 1
0,0>Board 1 I/O FPROM Test
0,0> I/O Board EPROM checksum Test
0,0>@(#) iPOST 3.4.27 2000/08/18 11:18
0,0> TESTING IO BOARD 1 ASICs
0,0> TESTING SysIO Port 0
0,0>Board 1 SysIO Registers Test
0,0> SysIO Register Initialization
0,0> IOMMU Registers and RAM Test
0,0> Streaming Buffer Registers and RAM Test
0,0> SBus Control and Config Registers Test
0,0> SysIO RAM Initialization
0,0>Board 1 SysIO Functional Test
0,0> Clear Interrupt Map and State Registers
0,0> SysIO Interrupts Test
0,0> SysIO Timers/Counters Test
0,0> IOMMU Virtual Address TLB Tag Compare Test
0,0> Streaming Buffer Flush Test
0,0> DMA Merge Buffer Test
0,0> SYSIO ECC Correctable Test
0,0> SYSIO ECC UnCorrectable Test
0,0> SysIO Sbus Probe Test
0,0> SysIO Register Initialization Test
0,0> SysIO RAM Initialization Test
0,0> Clear Interrupt Map and State Registers Test
0,0>Board 1 OnBoard IO Chipset (SOC) Test
0,0> SOC SRAM Test
0,0> SOC Registers Test
0,0> SOC Interrupt Test
0,0> Clear Interrupt Map and State Registers Test
0,0> TESTING SysIO Port 1
0,0>Board 1 SysIO Registers Test
0,0> SysIO Register Initialization
0,0> IOMMU Registers and RAM Test
0,0> Streaming Buffer Registers and RAM Test
0,0> SBus Control and Config Registers Test
0,0> SysIO RAM Initialization
0,0>Board 1 SysIO Functional Test
0,0> Clear Interrupt Map and State Registers
0,0> SysIO Interrupts Test
0,0> SysIO Timers/Counters Test
0,0> IOMMU Virtual Address TLB Tag Compare Test
0,0> Streaming Buffer Flush Test
0,0> DMA Merge Buffer Test
0,0> SYSIO ECC Correctable Test
0,0> SYSIO ECC UnCorrectable Test
0,0> SysIO Sbus Probe Test
0,0> SysIO Register Initialization Test
0,0> SysIO RAM Initialization Test
0,0> Clear Interrupt Map and State Registers Test
0,0>Board 1 OnBoard IO Chipset (FEPS) Test
0,0> FAS366 Registers Test
0,0> ESP FAS366 DVMA burst mode read/write Test
0,0> FAS366 FIFO TO DMA Test
0,0> DMA TO FAS366 FIFO Test
0,0> FEPS (Ethernet) Registers Test
0,0> FEPS Ethernet(BM, DP83840, Twister) Internal Loopbacks Test
0,0> SysIO Register Initialization Test
0,0> SysIO RAM Initialization Test
0,0> Clear Interrupt Map and State Registers Test
0,0>IO BOARD 1 TESTED
0,0>SYSTEM LEVEL TESTING
0,0>Board 0 Cache Coherency Test
0,0> Multi-Processor Cache Coherence Test
0,0> Testing CPU MID 1
0,0> Testing CPU MID 4
0,0> Testing CPU MID 5
0,0> Testing CPU MID 8
0,0> Testing CPU MID 9
0,0> Testing CPU MID 10
0,0> Testing CPU MID 11
0,0> Testing CPU MID 12
0,0> Testing CPU MID 13
0,0> Testing CPU MID 14
0,0> Testing CPU MID 15
0,0>Probing for Disk System boards
0,0>Board 0 System Interrupts Test
0,0> System Interrupts Test
0,0>Checking Power Supply Configuration
0,0>Power is more than adequate, load 7 ps 5
0,0> Check Board Present Test
0,0> Board Present Interrupt Test
0,0>
0,0> System Board Status
0,0>-----------------------------------------------------------------
0,0> Slot Board Status Board Type Failures
0,0>-----------------------------------------------------------------
0,0> 0 | Normal |+CPU/Memory |
0,0> 1 | Normal |+IO Type 4 |
0,0> 2 | Normal |+CPU/Memory |
0,0> 3 | Normal | Disk Board |
0,0> 4 | Normal |+CPU/Memory |
0,0> 5 | Normal |+CPU/Memory |
0,0> 6 | Normal |+CPU/Memory |
0,0> 7 | Normal |+CPU/Memory |
0,0> 16 | Normal | Clock Board |
0,0>-----------------------------------------------------------------
0,0>
0,0> CPU Module Status
0,0>-----------------------------------------------------------------
0,0> MID OK Cache Speed Version
0,0>-----------------------------------------------------------------
0,0> 0 | y | 8192 | 400 | 00170011.a0000507
0,0> 1 | y | 8192 | 400 | 00170011.a0000507
0,0> 4 | y | 8192 | 400 | 00170011.a0000507
0,0> 5 | y | 8192 | 400 | 00170011.a0000507
0,0> 8 | y | 8192 | 400 | 00170011.a0000507
0,0> 9 | y | 8192 | 400 | 00170011.a0000507
0,0> 10 | y | 8192 | 400 | 00170011.a0000507
0,0> 11 | y | 8192 | 400 | 00170011.a0000507
0,0> 12 | y | 8192 | 400 | 00170011.a0000507
0,0> 13 | y | 8192 | 400 | 00170011.a0000507
0,0> 14 | y | 8192 | 400 | 00170011.a0000507
0,0> 15 | y | 8192 | 400 | 00170011.a0000507
0,0>-----------------------------------------------------------------
0,0>System Frequency (MHz),fcpu=400, fmod=200, fsys=100, fgen=400
0,0> Populated Memory Bank Status
0,0> bd # Size Address Way Status
0,0> 0 1024 0 8 Normal
0,0> 0 1024 6 8 Normal
0,0> 2 1024 1 8 Normal
0,0> 2 1024 7 8 Normal
0,0> 4 1024 2 8 Normal
0,0> 4 1024 0 4 Normal
0,0> 5 1024 3 8 Normal
0,0> 5 1024 1 4 Normal
0,0> 6 1024 4 8 Normal
0,0> 6 1024 2 4 Normal
0,0> 7 1024 5 8 Normal
0,0> 7 1024 3 4 Normal
0,0>
0,0> Disk Board Status
0,0>-----------------------------------------------------------------
0,0>Slot Sckt0 Sckt1
0,0>-----------------------------------------------------------------
0,0> 3 Disk10 Disk11
0,0>
0,0>
0,0>
POST COMPLETE
0,0>Entering OBP

Switching to high addresses
Setting up TLBs Done
MMU ON
PC = 0000.01ff.f000.1cb8
PC = 0000.0000.0000.1d24
Decompressing into Memory Done
Size = 0000.0000.0006.d8c0
ttya initialized
Using POST's System Configuration
Setting up memory
Starting CPU ID 1
Starting CPU ID 4
Starting CPU ID 5
Starting CPU ID 8
Starting CPU ID 9
Starting CPU ID 10
Starting CPU ID 11
Starting CPU ID 12
Starting CPU ID 13
Starting CPU ID 14
Starting CPU ID 15
fhc ac simm-status environment sram flashprom SUNW,UltraSPARC-II SUNW,UltraSPARC
-II
fhc ac simm-status environment sram flashprom SUNW,UltraSPARC-II SUNW,UltraSPARC
-II
fhc ac simm-status environment sram flashprom SUNW,UltraSPARC-II SUNW,UltraSPARC
-II
fhc ac simm-status environment sram flashprom SUNW,UltraSPARC-II SUNW,UltraSPARC
-II
fhc ac simm-status environment sram flashprom SUNW,UltraSPARC-II SUNW,UltraSPARC
-II
fhc ac simm-status environment sram flashprom SUNW,UltraSPARC-II SUNW,UltraSPARC
-II
disk-board
Probing UPA Slot at 2,0 sbus fhc ac environment flashprom eeprom sbus-speed co
unter-timer
Probing UPA Slot at 3,0 sbus counter-timer
Probing /sbus@2,0 at d,0 SUNW,socal sf ssd sf ssd
Probing /sbus@2,0 at 1,0 Nothing there
Probing /sbus@2,0 at 2,0 Nothing there
Probing /sbus@3,0 at 3,0 SUNW,hme SUNW,fas sd st
Probing /sbus@3,0 at 0,0 cgsix
Using POST's System Configuration
Setting up memory
Starting CPU ID 1
Starting CPU ID 4
Starting CPU ID 5
Starting CPU ID 8
Starting CPU ID 9
Starting CPU ID 10
Starting CPU ID 11
Starting CPU ID 12
Starting CPU ID 13
Starting CPU ID 14
Starting CPU ID 15
fhc ac simm-status environment sram flashprom SUNW,UltraSPARC-II SUNW,UltraSPARC
-II
fhc ac simm-status environment sram flashprom SUNW,UltraSPARC-II SUNW,UltraSPARC
-II
fhc ac simm-status environment sram flashprom SUNW,UltraSPARC-II SUNW,UltraSPARC
-II
fhc ac simm-status environment sram flashprom SUNW,UltraSPARC-II SUNW,UltraSPARC
-II
fhc ac simm-status environment sram flashprom SUNW,UltraSPARC-II SUNW,UltraSPARC
-II
fhc ac simm-status environment sram flashprom SUNW,UltraSPARC-II SUNW,UltraSPARC
-II
disk-board
Probing UPA Slot at 2,0 sbus fhc ac environment flashprom eeprom sbus-speed co
unter-timer
Probing UPA Slot at 3,0 sbus counter-timer
Probing /sbus@2,0 at d,0 SUNW,socal sf ssd sf ssd
Probing /sbus@2,0 at 1,0 Nothing there
Probing /sbus@2,0 at 2,0 Nothing there
Probing /sbus@3,0 at 3,0 SUNW,hme SUNW,fas sd st
Probing /sbus@3,0 at 0,0 cgsix

8-slot Sun Enterprise E4500/E5500, No Keyboard
OpenBoot 3.2.30, 12288 MB memory installed, Serial #12391910.
Copyright 2002 Sun Microsystems, Inc. All rights reserved

{0} ok

Message was edited by:
sebskyman