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Can you upgrade the firmware version on the Workstation?
Patch 10360070: Ultra 40 M2 SW 1.6.0
12-MAY-09 Long Description:
Sun Ultra 40 M2 Workstation Software Supplemental 1.6.0
BIOS version 1.25
NVIDIA FX1700 VBIOS 60.84.74.00.21
When to Download:
BIOS 1.25 is to fix memory detection issue under Windows XP 32 bit. If the system is installed with NVIDIA FX1700 card, the VBIOS should be also updated.
Note: This release is for BIOS and VBIOS update only.
Cross-posted to other forum web sites.
That's bad forum etiquette.
Why should anyone bother to respond and possibly duplicate what you've been told elsewhere?
@rukbat - I am sorry if I have offended you rukbat. I was in urgent need of answers so I posted in 2 forums to get the earliest response.
As you can see there has been no response in the other forum. Had there been, I would have posted in this forum the resolution strategy.
@ Suriv - I am unable to power up the system. Because of the clicking sound the system seems grounded and could not power up.
I tried PC power supply tester on the PSU it powered up and has LEDS on all voltages except -5V which I think is normal as looking at the ACBEL 300-1800-02 PSU specs sticker there is no mention of -5V in this PSU.
So I am thinking it is a motherboard issue. I also tried resetting CMOS via jumper but it did not help as well.
Any advise would be appreciated. Thanks again.
"PWRCR11" can be... (See 11h post code, table 2-2)
Ultra™ 40 Workstation
Service Manual (For Ultra 40 and Ultra 40 M2)
Chapter 2.3 (page 2-7) Ultra 40 and Ultra 40 M2Workstation POST Codes
The following table lists descriptions of system POST codes in the order in which
they are generated. These POST codes appear as two digit hexidecimal output
(unless specified otherwise) either to the server’s display or LED display on the
During POST, the BIOS outputs the error code to I/O port 80h. The workstation
motherboard is equipped with a two segment LED display that displays the current
value of port 80h.
If the BIOS detects a terminal error condition, it issues a terminal-error beep code,
attempts to display the error code on upper left corner of the screen and on the port
80h LED display, and halts POST. If the system hangs before the BIOS can process
the error, the value displayed at port 80h is the last test performed.
TABLE 2-2 Ultra 40 and Ultra 40 M2 POST Codes
Code Beeps Description
04 Get CPU type from CPU registers and other methods. Save CPU type in
NVRAM. NOTE: Hook routine should not alter DX, which
holds the powerup CPU ID..
06 Initialize system hardware. Reset the DMA controllers, disable the videos,
clear any pending interrupts from the real-time clock and set up port B
07 Disable system ROM shadow and start to execute ROMEXEC code from
the flash part. This task is pulled into the build only when the ROMEXEC
relocation is installed.
08 Initialize chip set registers to the Initial POST Values.
09 Set in-POST flag in CMOS that indicates we are in POST. If this bit is not
cleared by postClearBootFlagJ (AEh), the BIOS on next boot determines
that the current configuration caused POST to fail and uses default values
Clear the CMOS diagnostic byte (register E). Check the real-time clock and
verify the battery has not lost power. Checksum the CMOS and verify it
has not been corrupted (Rel. 6.0).
0A Initialize CPU registers.
0B Enable CPU cache. Set bits in cmos related to cache.
0C Set the initial POST values of the cache registers if not integrated into the
0E Set the initial POST values for registers in the integrated I/O chip.
0F Enable the local bus IDE as primary or secondary depending on other
10 Initialize Power Management.
*11 General dispatcher for alternate register initialization. Set initial POST*
values for other hardware devices defined in the register tables.
12 Restore the contents of the CPU control word whenever the CPU is reset.
13 Early reset of PCI devices required to disable bus master. Assumes the
presence of a stack and running from decompressed shadow memory.
14 Verify that the 8742 keyboard controller is responding. Send a self-test
command to the 8742 and wait for results. Also read the switch inputs
from the 8742 and write the keyboard controller command byte.
16 1-2-2-3 Verify that the ROM BIOS checksums to zero.
17 Initialize external cache before autosizing memory.
18 Initialize all three of the 8254 timers. Set the clock timer (0) to binary count,
mode 3 (square wave mode), and read/write LSB then MSB. Initialize the
clock timer to zero. Set the RAM refresh timer (1) to binary count, mode 2
(Rate Generator), and read/write LSB only. Set the counter to 12H to
generate the refresh at the proper rate. Set sound timer (2) to binary count,
mode 3, and read/write LSB, then MSB.
1A Initialize DMA command register with these settings:
1. Memory to memory disabled
2. Channel 0 hold address disabled
3. Controller enabled
4. Normal timing
5. Fixed priority
6. Late write selection
7. DREQ sense active
8. DACK sense active low.
Initialize all 8 DMA channels with these settings:
1. Single mode
2. Address increment
3. Auto initialization disabled (channel 4 - Cascade)
4. Verify transfer
1C Initialize interrupt controllers for some shutdowns.
20 1-3-1-1 Verify that DRAM refresh is operating by polling the refresh bit in PORTB.
22 1-3-1-3 Reset the keyboard.
24 Set segment-register addressibility to 4 GB.
F1 Initialize Run Time Clock.
F2 Initialize video.
F3 Initialize System Management Modem.
F4 1 Output one beep.
F5 Boot to Mini DOS.
F6 Clear Huge segment.
F7 Boot to Full DOS.