1 Reply Latest reply: May 10, 2011 12:41 PM by 860881 RSS

    RTL simulations with actual workload

    859307
      Hi,
      I wish to simulate the OpenSPARC (T2) RTL and collect the trace data. I have set up the design and verification environment for OpenSPARC and am able to collect traces based on the tests in the regression suite. However, I want to simulate the RTL based on the actual workloads (benchmarks applications like MiBench, SPEC, etc.).
      Is it enough to cross-compile a benchmark C program and use the resulting .s file in place of the existing .s test files? I can then run sims with the full chip environment. Will this approach work? If somebody has tried this out, please do let me know.

      Thanks,
      Jay.
        • 1. Re: RTL simulations with actual workload
          860881
          Hey Jay


          Looks like you were successfully able to get activity information corresponding to the full chip using the available test benches(cmp1,cmp8,fc1 and fc8) in the package that is provided in OpenSparcT2.

          I don't have an answer to your question since I haven't tried anything like that yet. But hope to once I am able to overcome problems I have currently.

          I used the DV guide for Opensparc T2 as initial guide but in addition to it had to do a lot of debugging to set up the verification environment. What changes did you have to do get your simulation up and running?- could you elaborate on this. In particular I to compile certain libraries for the 64 bit environment because of some compatibility issues with gcc etc. Did you also encounter such problems?

          I am using this command

          sims -sim_type=vcs -novera_build -novera_run -debug_all -sys=cmp8 -group=cmp8_mini_T2 -novcs_use_fsdb -vcd -vcdfile=test.vcd


          Thanks,

          Sharat