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0 Replies Latest reply: Jun 14, 2011 12:30 AM by 868657 RSS

OpenSPARC synthesis and Simulation

868657 Newbie
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Hi all
I'm a student who is working on power modeling project
And I was suggested to use SPARC architecture which needs synthesis and simulation of OpenSPARC T1
So I started synthesis and was able to synthesize individual blocks successfully on Synopsys DCCompiler
Now I want to simulate the netlist using modelsim
The problem is I am not able to give proper inputs to the signals of vhdl test benches.(like inq signals of fpu_add )
Please suggest me where I can get the detailed explanation about the signals and various test cases for them
Thankyou in advance

P.S. : I tried enough with the test cases provided by OpenSPARC but VERA has some compatibility issues with Linux... As of now I want to know inputs for fpu_add module.

Edited by: 865654 on Jun 14, 2011 12:29 AM


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