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0 Replies Latest reply: Jul 20, 2011 2:31 AM by 876701 RSS

ASI_REAL disables L1 cache

876701 Newbie
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Hello everybody!

When executing a load or a store, I need to be able to specify the physical address.
I have tried using the ASI_REAL and ldxa and stxa operation.
This configuration makes it possible to specify the physical address (or the virtual address), however, through the PIC I have seen that, for every load, a miss in the L1 cache is counted, even if the data is supposed to be in L1 cache. Therefore, I think the L1 cache is disabled for this kind of operations.
Is that true?
Is there any way to specify the physical address without disabling the L1 cache?

I have also another doubt about the replacement policy in data L1 and L2. For the L2, the description given in the Micr_Arch pdf file is not clear.
Does anyone know the details about the LRU in data L1 and L2?



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