T5x20, T5x40 DIMM failure at POST
I'm looking for some document which describes about DIMM failure at POST of T5x20 and T5x40.
I know DIMM failure at POST will cause disabling two or 4 pieces DIMM at once however I do not know about the rule in detail
I'd appreciate if Oracle has useful document in MOS or community.
Thank you very much
Tomonori-